University of Wisconsin Madison
Digital System Design and Synthesis (E C E 551) Syllabus
Course Learning Outcomes
    Course Learning Outcome
  • 1
    Develop ability to use a hardware description language, simulation, and a logic synthesis tool in the design and verification of digital circuits
  • 2
    Understand design in a contemporary environment resulting from the use of deep-submicrometer implementation technologies and design reuse.
Details
Digital System Design and Synthesis
E C E 551 ( 3 Credits )
Description
Introduction to the use of hardware description langages and automated synthesis in design. Advanced design principles. Verilog and VHDL description languages. Synthesis from hardware description languages. Timing-oriented synthesis. Relation of integrated circuit layout to timing-oriented design. Design for reuse.
Prerequisite(s)
ECE/Comp Sci 352 & Jr st
Department: ELECTRICAL AND COMPUTER ENGR
College: College of Engineering
Instructor
Instructor Name
Instructor Campus Address
instructorEmail@emailaddress.edu
Contact Hours
3.5
Course Coordinator
MICHAEL MORROW
Text book, title, author, and year
Verilog HDL: a guide to digital design synthesis; Palnitkar; 2nd; 2003
Supplemental Materials
None
Required / Elective / Selected Elective
Selected Elective
ABET Program Outcomes Associated with this Course
Program Specific Student Outcomes
 
Brief List of Topics to be Covered

REVIEW OF COMBINATIONAL AND SEQUENTIAL LOGIC DESIGN

STRUCTURAL MODELS OF COMBINATIONAL LOGIC

LOGIC SIMULATION

PROPAGATION DELAY

USER DEFINED PRIMITIVES

BEHAVIORAL MODELS OF COMBINATIONAL AND SEQUENTIAL LOGIC

SYNTHESIS OF COMBINATIONAL AND SEQUENTIAL LOGIC

DESIGN AND SYNTHESIS OF DATAPATH CONTROLLERS

ARITHMETIC PROCESSORS

POSTSYNTHESIS DESIGN TASKS

Additional Information
 
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