University of Wisconsin Madison
Design Automation of Digital Systems (E C E 556) Syllabus
Course Learning Outcomes
    Course Learning Outcome
  • 1
    Students will learn VLSI computer-aided design (CAD) flow, its various components and their interactions for modern chip design.
  • 2
    Students will be able to use dynamic programming to solve an instance of the technology mapping problem for netlist synthesis and minimizing area and delay.
  • 3
    Students will be learn about simulated annealing optimization framework and its effective implementation for chip floor planning using binary tree and sequence pair representations.
  • 4
    Students will be able to write Integer Linear Programming (ILP) formulations for variations of global routing problem targeting minimization of routing overflow and wirelength. They will learn practical considerations of using ILP for large industry-sized problems.
  • 5
    Students will learn the A* search algorithm for single-net routing and its impact as a core building block in a modern global routing framework.
  • 6
    Students will learn practical algorithms for circuit partitioning and detailed routing in modern chip design.
  • 7
    Students will learn the significance of various CAD techniques such as clock tree synthesis and power grid planning.
Design Automation of Digital Systems
E C E 556 ( 3 Credits )
Use of digital computers to simulate, partition, place and interconnect digital electronic systems.
ECE/Comp Sci 352; Comp Sci 367; or consent of instructor
College: College of Engineering
Instructor Name
Instructor Campus Address
Contact Hours
Course Coordinator
Text book, title, author, and year
"VLSI Physical Design: From Graph Partitioning to Timing Closure", Kahng, Lienig, Markov, Hu, 2011. "Logic Synthesis and Verification Algorithms", Hachtel, Somenzi, 2000.
Supplemental Materials
Required / Elective / Selected Elective
Selected Elective
ABET Program Outcomes Associated with this Course
Program Specific Student Outcomes
Brief List of Topics to be Covered
  1. Overview of VLSI design flow, styles, and computational complexity
  2. Technology mapping (using dynamic programming)
  3. Introduction to Static Timing Analysis
  4. Circuit partitioning
  5. Floorplanning (using simulated annealing)
  6. Placement
  7. Global routing (using A* shortest path algorithm, and integer linear programming)
  8. Detailed routing (using Dijkstra's algorithm, and left-edge algorithm)
  9. Overview of Clock Tree Synthesis
  10. Overview of power grid planning
Additional Information
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