University of Wisconsin Madison
Introduction to Computer Architecture (E C E 552) Syllabus
Course Learning Outcomes
    Course Learning Outcome
  • 1
    Students will be able to use standard performance metrics to compare performance of different digital systems
  • 2
    Students will be able to design a pipelined data path for a RISC (reduced instruction set computer) instruction set and be familiar with concepts of data dependence, pipelined hazards and out of order execution.
  • 3
    Students will be able to design basic data and control cache subsystems and understand basic memory organization
  • 4
    Students will be able to design a pipelined RISC micro-processor system with data cache using computer aided design tool and validate the correctness of the design using logic simulation.
Introduction to Computer Architecture
E C E 552 ( 3 Credits )
The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures. E C E 551 or knowledge of Verilog is recommended.
(COMP SCI/E C E 352 and COMP SCI/E C E 354) or graduate or professional standing
College: College of Engineering
Instructor Name
Instructor Campus Address
Contact Hours
Course Coordinator
Text book, title, author, and year
Computer Organization and Design: The Hardware/Software Interface; Patterson & Hennessy; 4th; 2011
Supplemental Materials
Required / Elective / Selected Elective
Selected Elective
ABET Program Outcomes Associated with this Course
Program Specific Student Outcomes
Brief List of Topics to be Covered
  1. Introduction, basic computer organization
  2. Instruction formats, instruction sets and their design
  3. ALU design: Adders, subtracters, logic operations
  4. Datapath design
  5. Control design: Hardwired control, microprogrammed control
  6. More on arithmetic: Multiplication, division, floating point arithmetic
  7. RISC machines
  8. Pipelining
  9. Memory systems and error detection and error correction coding
  10. I/O
Additional Information
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