University of Wisconsin Madison Digital System Fundamentals (E C E 352) Syllabus Course Learning Outcomes Course Learning Outcome 1 Students will learn how to design combinational logic circuits 2 Students will learn how the fundamentals of sequential logic circuits 3 Students will learn the primary components of a simple CPU architecture 4 Students will learn how to use modern CAD tools and FPGAs to implement digital circuits. Details Digital System Fundamentals E C E 352 ( 3 Credits ) Description Logic components, Boolean algebra, combinational logic analysis and synthesis, synchronous and asynchronous sequential logic analysis and design, digital subsystems, computer organization and design. Prerequisite(s) Comp Sci/ECE 252 Department: ELECTRICAL AND COMPUTER ENGR College: College of Engineering Instructor Instructor Name Instructor Campus Address instructorEmail@emailaddress.edu Contact Hours 5.5 Course Coordinator KRACHEY, JOSEPH S Text book, title, author, and year Logic and Computer Design Fundamentals; Mano and Kime; 4; 2007Logic and Computer Design Fundamentals; Mano & Kime; 4; 2007 Supplemental Materials None Required / Elective / Selected Elective Required ABET Program Outcomes Associated with this Course 1 A An ability to apply knowledge of mathematics, science, and engineering 2 B An ability to design and conduct experiments, as well as to analyze and interpret data 3 C An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability 4 E An ability to identify, formulate, and solve engineering problems 5 G An ability to communicate effectively 6 K An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice Program Specific Student Outcomes Brief List of Topics to be Covered Binary, Octal, Hexadecimal number systems Boolean Algebra Combination circuit design Sequential circuit design and timing analysis Finite state machines Data path design Control path design SRAM operation Single Cycle CPU design Additional Information Printed: Oct 23, 2017 1:13:15 AM Generated by AEFIS. Developed by AEFIS, LLC Copyright © University of Wisconsin Madison 2017. All rights reserved.